1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device in which an epitaxial layer is provided on a semiconductor substrate of high impurity concentration and has an impurity concentration lower than that of the semiconductor substrate.
2. Description of the Background Art
FIG. 13 is a cross section showing a partial structure of a DRAM (Dynamic Random Access Memory) in which an epitaxial layer is provided on a semiconductor substrate, as an example of the background art. In the DRAM of FIG. 13, a p-type epitaxial layer 2 (referred to as "p.sup.- epitaxial layer" hereinafter) is provided on a p-type semiconductor substrate 1 of high impurity concentration (referred to as "p.sup.++ substrate" hereinafter) and has an impurity concentration lower than that of the p.sup.++ substrate, a p well 3 is formed in a portion of the p.sup.- epitaxial layer 2 and n.sup.+ diffusion layers 4a and 4b are selectively formed in the p well 3. A memory cell capacitor 5 is connected onto the n.sup.+ diffusion layer 4b. The n.sub.+ diffusion layers 4a and 4b serving as source and drain constitute a transistor, with a gate electrode 8. On the other hand, an n.sup.+ diffusion layer 6 is selectively formed in the p.sup.- epitaxial layer 2 separately from the p well 3, to which an external signal input circuit 7 is connected.
In the background-art DRAM, when minority carriers (electrons in a p-type epitaxial layer and positive holes in an n-type epitaxial layer) injected to the p.sup.- epitaxial layer 2 from the external signal input circuit 7 through the n.sup.+ diffusion layer 6 reach the n.sup.+ diffusion layer 4b via the p.sup.- epitaxial layer 2, electric charges accumulated in the memory cell capacitor 5 decrease to cause a loss of stored information. That results in a failure of the DRAM.
In the structure where the p.sup.- epitaxial layer 2 is provided on the p.sup.++ substrate 1 of higher impurity concentration as shown in FIG. 13, particularly, the minority carriers injected to the p.sup.- epitaxial layer 2 from the external signal input circuit 7 are reflected from an interface between the p.sup.- epitaxial layer 2 and the p.sup.++ substrate 1 under the influence of an internal potential caused by a difference in impurity concentration between the p.sup.- epitaxial layer 2 and the p.sup.++ substrate 1, never entering the p.sup.++ substrate 1, and then captured in the n.sup.+ diffusion layer 4a, 4b or the p well 3. That disadvantageously leads to an increase in failure of the DRAM due to the injection of the minority carriers.